John DeRoo
2029 Silvastone Drive NE
Atlanta, GA 30345
jderoo@alum.mit.edu
Summary
Technologist with 30+ years of development and management experience, 20+ issued patents, and numerous products brought to market in multiple fields such as controlled environment agriculture, small form factor displays, network infrastructure, 3D graphics, office automation, and hard disk drives. International experience in Japan, Korea, Taiwan, Switzerland, Germany, Austria, Israel, Oman, and Canada.
Experience
Agrify Corporation, Burlington, MA
1/2020 - 1/2021 Vice President Systems Engineering leading a multi-disciplinary engineering team developing and implementing technology for Controlled Environment Agriculture. Continued the work from TriGrow and added responsibility for managing the Engineering team, developing and improving the growth chambers, and interfacing with manufacturing.
TriGrow Systems, Greater Atlanta Area, GA
purchased by Agrify
4/2019 - 1/2020 Chief Technology Officer at a spin-off of Agrinamics (see below) developing and deploying Controlled Environment Agriculture solutions targeted at commercial-scale legal Cannabis production. Worked with customers, suppliers, horticulture experts, and sales to develop and deploy entire ‘seed to harvest’ systems. Directly managed and debugged bring-up of previously installed systems and brought learnings back to suppliers for improvement of next-generation equipment and practices.
Eta Wireless, Cambridge, GA
5/2017 - 3/2019 Chief Digital Architect at a spin-off of Eta Devices (see below) developing IP for high efficiency radio transmitters used in handsets. Architected and implemented the top level andf the Digital Data Path of the IP using Verilog, System Verilog, SRDL, Make, Python, JSON, Git, and targeting the design for both ASIC and Xilinx SoC implementations. Rearchitected and reimplemented the digital portion of a Mixed Signal Power Management IC. Worked closely with RF, Power, and DSP engineers as well as customer engineering teams to pull all aspects of the system together.
PodPonics/Agrinamics,
Atlanta, GA
PodPonics changed its name
to Agrinamics in mid 2016
11/2014 - 10/2016 Chief Technology Officer & Vice President of Engineering in a startup producing the technology to hydroponically grow produce in controlled environments. Lead the team developing new systems technologies for lighting, irrigation, and environment control using IoT technologies. Worked with development partners in the US and Japan. Developed the control system architecture and several of the control and monitoring components. Personally supervised deployment of the technology to farms in the US and Oman.
Eta Devices, Cambridge, MA
2/2012 - 12/2013 Chief Digital Architect in an MIT startup developing high efficiency transmitter technology for basestation and handset applications. Architected digital system, implemented second generation development platform in FPGA, designed and oversaw implementation of the third generation FPGA development platform, and developed the plan to complete prototype development and transition the design to an ASIC implementation.
Pixtronix, Andover, MA
12/2008 -12/2011 Director of Control Systems team developing ASICs, controller boards, TFT-backplane control circuits, and user interface software for high-quality, low-power, small and medium form factor MEMS-based display systems. Architected second generation display development controller system. Managed the design, layout, and fabrication of the boards; the development of the FPGA code; and the development of the Graphical User Interface code. Negotiated functional specifications with other functional teams. Worked closely with technical partners in Japan, Korea, and Taiwan using a combination of face-to-face meetings, teleconferences, and email. Travelled frequently to Asian partners' facilities for meetings, to provide training, and to provide support. Worked with team members to generate and monitor development schedules. Managed hiring and onboarding of new employees.
12/2007 - 12/2008 Manager of ASIC Development for the development of control ASICs used in low-power, high quality displays for handheld devices. Developed architecture and chip specs for a Chip-On-Glass driver ASIC with a team in Switzerland, monitored and coordinated the chip implementation, and supervised the testing of the chip. Responsible for display technology demo preparation and deployment at trade shows in Asia and the US.
Systems Group, Sun Microsystems, Inc., Burlington, MA
6/2004 - 11/2007 Engineering Manager of the 8 person Network Systems Group east-coast chip engineering team. Managed design, verification, and debug work on all FPGAs in all versions of the Sun Secure Application Switch. Managed architecture, design, and verification of programmable chips used for power management and hot-plug control of the processor blades in the Sun Blade 8000 Modular System. Coordinated and managed development of the control plane chips used in several Network Express Modules for the SB8000.
1/2004 - 6/2004 Senior Staff Engineer in the Network Systems Group, continuing the work from Nauticus on the Sun Secure Application Switch family. Produced cost-reduced version of the Stream Memory Manager used in the Sun Secure Application Switch N1000 Series. Worked on architectural definition of next-generation switch.
ASIC Design Team, Nauticus Networks, Framingham, MA
Purchased by Sun
1/2001 - 1/2004 Principal Design Engineer in a networking startup creating powerful infrastructure products to deliver the next generation internet. Designed a 64GB Stream Memory Manager FPGA written in Verilog. Responsible for architectural definition, implementation, and functional and performance testing. Worked closely with System Architect and other chip designers to define the Data Flow Architecture used for communications between the chips and the software running on Network Processors.
3D Hardware Design Team, ATI Technologies, Marlborough, MA
4/99 - 12/2000 Hardware Manager of a 25 person ASIC design team working on three to four concurrent projects. Responsible for performance reviews, scheduling, resource allocation, long-term resource planning, and daily management of the team. Primary Hardware Manager for all of the Radeon graphics functionality, which was developed across three sites. Responsible for direct management of local design team, coordination of development schedules with the teams at other sites, resolution of multiple-customer issues, and communication between marketing, architecture, senior management, and the design teams.
4/98 - 3/99 Hardware Project Technical Lead of the team developing the Radeon. Gave technical direction to a team of 30 hardware designers at two sites. Developed and documented design methodologies and processes, and tested new tools and flows. Coordinated and scheduled development of documentation, HDL design, and synthesis. Directly interfaced with the layout team. Mentored new hires. Refined a data manipulation mechanism and worked closely with attorneys on several patent applications.
3/97 - 3/98 Senior Hardware Designer in a team developing high performance graphics accelerators for the PC and Mac markets. Designed and implemented deeply pipelined multi-port Pixel Cache for Rage128. Coordinated work of designers in Toronto. Generated documentation and refined patent applications. Synthesized portions of the design using Synopsys, and tested the design using QuickTurn Hardware Emulator.
ASIC Design Group, Pixel Magic, Andover, MA
4/96 - 3/97 Senior ASIC Designer in a small team implementing the PM35/ PM36 JPEG codec in standard-cell silicon with VHDL and datapath methodologies. Designed, implemented, tested, synthesized, and optimized three of the five primary functional blocks in a very high speed semicustom JPEG endec chip.
Technology and Engineering Group, Quantum Corporation, Shrewsbury, MA
10/94 - 3/96 Project Leader of a 22 person team designing and implementing the disk controller chip for Quantum's high-end SCSI disk, the Atlas II
Disk and Subsystems Group, Digital Equipment Corporation, Shrewsbury, MA
purchased by Quantum
1/94 - 10/94 Project Leader of a six person team implementing a very high speed PRML detector chip intended for the read-chain of Digital's next generation of disks.
3/93 - 1/94 Contributing Member of three person team working on a disk controller chip that interfaced to the AT bus.
2/92 - 3/93 Project Leader of a five person team implementing Digital's next generation of disk controller chip.
5/90 - 2/92 Lead Engineer of five person team developing Digital's first banded hard disk controller chip.
1/89 - 4/90 Contributing Member of four person team converting and improving a custom hard disk controller chip from full-custom NMOS to a CMOS gate array.
6/87 - 12/88 Contributing Member of three person team developing a standard cell ASIC interface to Digital's proprietary SCSI-like bus (DSSI).
Skills
- FPGA, Gate Array, Standard Cell, and Custom high speed CMOS ASIC architecture, design, and development with schematic and HDL methodologies (Verilog, System Verilog, VHDL)
- Technical management of hardware and software development
- Leadership of multi-site international technical development
- Project management, including use of MS Project, MS Office, Visio, etc.
- Professional Association of Diving Instructors (PADI) IDC Staff Instructor.
- International Association of Nitrox and Technical Divers (IANTD) Advanced Recreational Trimix Instructor
Formal Education
1988 - 1990 Worcester Polytechnic Institute Graduate classes in digital circuits and systems design and signal processing.
1987 - 1994 Digital Equipment Corporation Education and Training Classes on Digital Systems Design, Error Correcting Codes, Coding Theory, C++, etc.
1983 - 1987 Massachusetts Institute of Technology Bachelor of Science in Electrical Engineering.
Issued US Patents
note that several of these
are continuations
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19 May 2020 |
Linearization circuits and methods for multilevel power amplifier systems |
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25 December 2018 |
Linearization circuits and methods for multilevel power amplifier systems |
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31 July 2018 |
RF amplifier having a transition shaping filter |
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8 November 2016 |
RF amplifier having a transition shaping filter |
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19 January 2016 |
Circuits for controlling display apparatus |
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8 December 2015 |
RF amplifier having discrete supply voltages |
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27 October 2015 |
Method and apparatus for multilevel power amplification |
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20 October 2015 |
Transmitter architecture and related methods |
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13 October 2015 |
Linearization circuits and methods for multilevel power amplifier systems |
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28 April 2015 |
RF amplifier architecture and related techniques |
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9 September 2014 |
Linearization circuits and methods for multilevel power amplifier systems |
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2 September 2014 |
RF amplifier architecture and related techniques |
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27 June 2006 |
Stream based memory manager with function specific hardware logic for accessing data as a stream in memory |
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2 December 2003 |
Method and apparatus for accessing graphics cache Memory |
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5 November 2002 |
Method and apparatus for compressing parameter values for pixels in a display frame |
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25 September 2001 |
Method and apparatus for assuring cache coherency |
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21 August 2001 |
Method and apparatus for association of memory locations with a cache location having a flush buffer |
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30 January 2001 |
Method and apparatus for arbitrating access requests to a memory |
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9 January 2001 |
Method and apparatus for accessing graphics cache memory |
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12 November 1996 |
Method and apparatus for encoding data with variable block lengths |
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11 January 1994 |
Embedded servo banded format for magnetic disks for use with a data processing system. |
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26 January 1993 |
Method and apparatus for transferring data between a data bus and a data storage element. |